Physical Design Engineer

About The Role

Broadcom’s ASIC Products Division (APD) is looking for a motivated Physical Design Engineer (NCG) to join our Physical Design team. In this role, you will work alongside experienced engineers in executing the implementation tasks for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs. In this role, you will gain hands-on experience in complex block-level floorplanning, synthesis, Place and Route (P&R), clock tree synthesis (CTS), timing closure, and signoff across cutting-edge deep sub-micron nodes (N5/N3/N2/A14).

Key Responsibilities

• Participate in block-level floorplanning, and run placement and route (P&R) flows using industry-standard EDA tools.
• Perform Static Timing Analysis (STA), debug timing paths, and execute ECOs for timing closure.
• Run Physical Verification checks (DRC, LVS, ERC, Antenna) and resolve signoff violations.
• Analyze IR drop and electromigration (EM) to ensure power grid integrity.
• Develop and maintain automated scripts (TCL, Python, Ruby) to enhance flow efficiency and productivity.

Requirements & Tech Stack

• Digital CMOS logic design, standard cell libraries, and semiconductor fundamentals.
• Static timing analysis (STA) concepts, clocking, and setup/hold timing.
• EDA design tools: Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime, or Siemens tools.
• Scripting languages: TCL, Python, Ruby, or Bash.

Qualifications

• Education:
• Bachelor's Degree in Electrical Engineering, Computer Engineering + 2yrs of experience.
• Master’s degree in Electrical Engineering, Computer Engineering (Graduation date within the past 12 months).
• Prior internship or research experience in ASIC physical design, synthesis, or physical verification.
• Basic understanding of Design for Testability (DFT), low-power intent (UPF/CPF), and FinFET technologies.
• Excellent problem-solving, debugging, and analytical skills.