Physical Design Engineer

About the Role

At IBM Infrastructure & Technology, we design and operate the systems that keep the world running.

Your Role and Responsibilities

We are looking for a highly skilled Physical Design Engineer with deep expertise in static timing analysis using Cadence Tempus. The ideal candidate will own timing closure across multiple blocks and top-level designs, working closely with synthesis, PD, and signoff teams to achieve high-performance, low-power SoC designs.

Key Responsibilities

• Lead timing closure strategy for full-chip / hierarchical SoC designs using ILM/ETM-based flows
• Own signoff correlation between Tempus and other tools (PrimeTime, Innovus, etc.)
• Drive timing closure across all PVT corners and MMMC modes; debug and resolve timing violations
• Define and enforce timing methodology guidelines across the team; mentor junior/mid-level engineers
• Develop and validate SDC constraints; perform timing ECOs (buffering, resizing, logic restructuring)
• Drive automation – develop reusable TCL/Python scripts for timing analysis, reporting, and waiver management
• Analyze SI, crosstalk, and noise issues; handle Tempus SI for crosstalk delta-delay and glitch analysis
• Interface with Cadence EDA vendor for tool issues and new feature adoption
• Participate in architecture and floorplan reviews to identify timing risks early
• Contribute to DFM and low-power (CPF/UPF) timing signoff; generate timing reports and signoff closure

Requirements & Tech Stack

• Cadence Tempus (hands-on)
• Strong STA fundamentals
• MMMC / OCV / AOCV / POCV
• SDC expertise
• Timing ECO methodology
• ILM / ETM / QRC models
• SPEF correlation & back-annotation
• Tempus SI (crosstalk / glitch)
• CTS timing implications
• Multi-Vt / voltage island timing
• Innovus–Tempus in-design timing
• Cadence Conformal ECO
• Unix / Linux & TCL / Python scripting
• Advanced nodes (12nm or below)
• Physical-aware Tempus experience

Preferred Qualifications

• Bachelor's Degree
• Experience with Cadence Innovus or other PD tools
• Understanding of IR/EM and power analysis impacts on timing
• Familiarity with low-power design techniques (UPF/CPF)
• Exposure to signoff methodologies and tapeout cycles
• Knowledge of automation and timing flow optimization