ASIC Physical Design Engineer

About the Role

Alpaca is building the full stack of hardware, software, models, and applications for personal AI. This is a full-time, on-site role at our Cambridge, MA office, starting in 2027. We are looking for master's and PhD graduates with strong fundamentals in digital IC design and substantial hands-on experience in ASIC physical implementation through research, internships or tapeout projects.

Key Responsibilities

• Implement assigned blocks through synthesis, floorplanning, placement, clock-tree synthesis and routing, using static timing analysis to guide timing closure.
• Analyze timing, congestion, area and power results; implement changes and measure their effects.
• Write Tcl and Python scripts to automate implementation steps, reproduce runs and summarize results.
• Contribute to SRAM macro placement, power-grid planning and physical verification for memory-intensive blocks.
• Work with RTL, verification and architecture engineers to understand how design choices affect physical implementation.
• Document results and unresolved issues, participate in design reviews, and take increasing responsibility for block deliverables.

Requirements & Tech Stack

• Experience taking a design from RTL or a netlist through place and route to a DRC-clean layout and closing timing, using Cadence, Synopsys or an open-source flow such as OpenROAD.
• Programming skills in Python and Tcl, and comfort working in Linux.
• Analytical and debugging skills, with the ability to explain implementation results, design tradeoffs and your own contributions clearly.

Qualifications

• A master's degree or PhD in Electrical Engineering, Computer Engineering or a related field, completed or expected between December 2026 and June 2027.
• Substantial hands-on ASIC physical design experience through research, coursework or an internship, with clear personal responsibility for implementation and debugging.
• Strong foundations in digital IC design, VLSI and computer architecture, including CMOS logic, synchronous design, setup and hold timing, clocking and interconnect delay.
• Contributions to a chip tapeout, with clear ownership of physical implementation tasks.
• Research in VLSI, physical design, EDA or computer architecture involving implemented and evaluated designs or tools.
• An internship in physical design, timing, verification or CAD.
• Experience with SRAM macros, power-grid planning, physical verification (DRC/LVS) or low-power design.
• Experience with open-source tools such as OpenROAD, Yosys, OpenSTA, KLayout or Magic.