Design Verification, Bangalore / Hyderabad
UST
Bengaluru, Karnataka, India2h agovia LinkedIn
Posted 13 Nov 2026, 16:39 IST
This job at a glance
- Who can apply
- Freshers
- Work
- On-site in Bengaluru
- Pay
- Not stated by the employer.
- Listed
- 13 Nov 2026 · still open
Key Responsibilities
- System Verilog based UVM Functional verification
- Behavioral modeling of functional blocks
- System-level performance verification, traffic patterns, bandwidth & latency analysis
- Develop and execute testbenches to validate the functionality and correctness of models
- Participate in system-level testing and debugging
- Setup verification environment and bring up simulations with various simulators such as VCS / Questa / Xcellium / Riviera
- SV/UVM Functional verification
- Simulation debugs using Vivado
Requirements & Tech Stack
- Expertise in AXI4 bus protocol
- Experience in Network On Chip (NOC) protocol
- Experience in multi-master, multi-slave AXI4 use-case configurations
- Knowledge of DRAM memory controllers