Associate II

About the Role

UST is seeking a PCIe Validation Engineer with hands-on experience in platform validation, board bring-up, and PCIe protocol testing. This role involves executing validation test plans, debugging issues, and supporting system-level validation of PCIe-based products.

Key Responsibilities

• Execute PCIe validation test cases on FPGA, emulation, or silicon platforms.
• Perform board bring-up, functional validation, and debug activities.
• Analyze logs, protocol traces, and test results to identify failures.
• Work closely with Design, Verification, Firmware, and Software teams to root-cause issues.
• Validate PCIe features including enumeration, link training, power management, MSI/MSI-X, and error handling.
• Document test execution, debug findings, and validation reports.

Requirements & Tech Stack

• 2+ years of experience in Validation, Silicon Validation, or Post-Silicon Testing.
• Good understanding of PCIe architecture and protocol fundamentals.
• Experience in executing validation test plans and debugging failures.
• Knowledge of digital electronics and computer architecture concepts.
• Strong debugging, problem-solving, and communication skills.
• Comfortable working in lab environments with hardware platforms.
• Linux commands and system-level debugging.
• Python or Shell scripting for test automation.
• Understanding of interfaces such as I2C, SPI, UART, AXI, or Ethernet.
• Experience with FPGA-based validation platforms.
• Exposure to protocol analyzers, oscilloscopes, and logic analyzers.
• Exposure to PCIe Gen4/Gen5/Gen6 validation is a plus.