RTL Power Optimization Engineer

About the Role

NVIDIA is defining the next era of computing with AI, where GPUs act as the brains of computers, robots, and self-driving cars. Our team is focused on the Power Optimization of Data center, gaming, and automotive GPU chips, as well as Networking chips. We provide architecture, micro-architecture, RTL Design, methodology, and AI-based power optimization solutions.

Key Responsibilities

• Use internally developed tools and industry-standard pre-silicon gate-level and RTL power analysis tools to improve product power efficiency.
• Use artificial intelligence to deliver RTL and/or Architecture Power optimization solutions.
• Develop and share best practices for performing pre-silicon power analysis.
• Perform comparative power analysis to identify trends and anomalies requiring further scrutiny.
• Interact with architects and RTL designers to help them interpret power data, identify power bugs, and drive implementation of fixes.
• Select and run a wide variety of workloads for power analysis.
• Prototype new architectural features in Verilog and analyze power.

Requirements & Tech Stack

• Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and common low-power design patterns at the RTL level.
• Knowledge of backend flows such as logic synthesis and place-and-route, and their impact on post-layout power and timing.
• Familiarity with RTL implementation of low-power techniques (e.g., clock gating, operand isolation, power gating strategies, multi-VT usage) and their trade-offs.
• Exposure to industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent.
• Strong Python programming skills for automation scripts, data pipelines, and AI/ML-driven analysis flows for RTL power optimization.
• Coursework and/or hands-on experience in Machine Learning and Artificial Intelligence, with the ability to apply ML techniques to EDA and silicon power problems.
• Previous experience debugging RTL or gate-level power anomalies.
• Strong written and verbal communication skills to document methodologies and present findings.

Qualifications

• Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, or related fields with coursework or experience in AI, Digital Design, and VLSI concepts (or equivalent experience).