Silicon Engineer
This job at a glance
- Who can apply
- New grads, no experience needed
- Must know
- Machine learningGCPCADCircuit designPythonC++
- Work
- On-site in Sunnyvale
- Pay
- Not stated by the employer.
- Skill demand
- Circuit design31%Machine learning14%CAD7%GCP2%of 99 similar entry-level jobs posted in the US this week
- Listed
- Nov 11, 2026 · still open
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About the Role
This role is for PhD graduates with completion dates in 2026 or 2027. The position involves working on AI/ML hardware acceleration, specifically driving TPU (Tensor Processing Unit) technology that powers Google's AI/ML applications. You will collaborate with engineers to influence the future of Google Cloud and AI infrastructure by working on foundational technology. Projects are tailored to individual expertise and can focus on any part of the system stack.
Key Responsibilities
- Responsibilities and projects will be determined based on your background, interest, and skills.
- Collaborate cross-functionally across hardware and software teams to research, design, and model custom silicon solutions and AI accelerators.
- Develop, simulate, and verify architectural features, digital blocks, or subsystem interfaces targeting performance, power, and area optimizations.
- Contribute to EDA design automation flows, tooling infrastructure, or post-silicon bring-up and characterization.
Requirements & Tech Stack
- PhD degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- Experience in any one domain of silicon engineering through internships, academic research, or publications: architecture and RTL, verification and validation, physical design and circuits, systems, test or CAD.
- Experience with one of the hardware description languages (e.g., Verilog, SystemVerilog) or programming languages (e.g., Python, Tcl, Perl, or C++).
Qualifications
- Research experience in specialized areas such as high-performance/low-power architectures, domain-specific accelerators (DSAs/TPUs), memory hierarchies, coherent interconnects (e.g., CXL, PCIe, UCIe, NoC), or advanced packaging/chiplets.
- Experience developing and maintaining CAD/EDA design flows, methodology infrastructure, or applying ML for chip design automation.
- Understanding of advanced ML/DL model architectures (e.g., Transformers, LLMs) with experience in performance modeling, cycle-accurate simulation, or custom AI accelerator evaluation.
- Familiarity with industry-standard EDA tools (e.g., from Synopsys, Cadence, Siemens EDA, or emulation/formal platforms).
- Demonstrated research track record and ability to work on complex, open-ended problems, with publications in conferences (e.g., ISCA, MICRO, HPCA, ASPLOS, DAC, ICCAD, ISSCC, NeurIPS, MLSys).