VLSI Design Verification Intern

About the Role

As an intern, you’ll work alongside experienced architects, logic designers, and verification engineers on a switch or NIC ASIC verification project for a future generation of HPE Slingshot. You’ll learn industry-standard SystemVerilog and UVM verification techniques, participate in technical design and debug discussions, and see how our team is applying emerging agentic AI workflows to solve complex engineering problems. We are looking for students interested in careers in design verification, HPC and AI systems, or high-performance interconnects.

Key Responsibilities

• Develop SystemVerilog and UVM testbench components, including models, monitors, scoreboards, and checkers
• Write constrained-random tests
• Develop and analyze functional coverage to identify verification gaps
• Debug regression failures and help identify, log, and resolve logic bugs
• Work directly with ASIC designers and architects
• Use scripting, automation, and AI-assisted tools to improve the verification process

Requirements & Tech Stack

• Pursuing a bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Coursework in digital design and computer architecture
• Experience with object-oriented programming
• Strong analytical and problem-solving skills
• Clear written and verbal communication skills
• Willingness to ask questions, explain your reasoning, and participate in technical discussions

Preferred Skills

• Experience with a hardware description language such as Verilog, SystemVerilog, or VHDL
• Experience with Python, Perl, Tcl, or another scripting language
• Experience working in Linux development environments
• Academic, research, or personal projects involving digital hardware
• Experience working as part of a distributed team
• Experience with agentic AI coding tools and workflows is preferred but not required.