AMSV junior engineer

About the Role

Position - AMSV junior engineer

Key Responsibilities

• Understand AMS simulation methodologies/flows (AXUM, AVUM, UVM-AMS).
• Review specifications, develop testcases independently as per the VPLAN.
• Have good debugging skills with respect to RTL, analog behavioral models and analog schematics.
• Gain hands-on technical experience in simulating testcases, debug SPICE and digital cosimulations for IPs, Subsystems and sub-blocks.
• Understand analog and digital design intent, ensure correct test conditions, bug finding and reporting.
• Analyze results using waveform/debug tools and identify root cause for functional mismatch.
• Create behavioral models in Verilog-A/AMS, SV-RNM, VHDL-AMS and capture the functionality closely matching the actual circuit behavior.
• Meet deadlines with high-quality deliverables.
• Actively upskill on the project, showing a learning curve and being proactive technically.

Requirements & Tech Stack

• Strong understanding of AMS verification methodologies, including mixed signal cosimulation, assertion and checkers-based verification.
• Proficiency in EDA tools such as Cadence Virtuoso, Synopsys VCS and related verification platforms.
• Good understanding of analog solver and simulator settings.
• Proficient in Systemverilog, UVM and analog behavioral modeling languages (SV-RNM/Verilog-AMS/Verilog-A).
• Strong fundamentals of Analog and Digital concepts.
• Hands-on experience with SPICE and digital simulation tools and debug environments.
• Comfortable working in a collaborative team setup with clear communication.
• Employ scripting languages (PERL, TCL, Python) for automation of tasks and efficiency in verification processes.