Silicon Trainee
DECCANX
Bengaluru, Karnataka, IndiaFresher3h agovia LinkedIn
This job at a glance
- Who can apply
- Freshers and up to 1 year · B.Tech / B.E.
- Must know
- GitLinuxPython
- Work
- On-site in Bengaluru
- Pay
- Not stated by the employer.
- Skill demand
- Python36%Git22%Linux11%of 99 similar fresher jobs posted in India this week
- Listed
- 1 Nov 2026 · still open
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About the Role
The Silicon Trainee role is a structured entry point for B.Tech ECE VLSI and AEXP graduates who want to see the whole flow from specification to timing before choosing where to specialise. You will rotate through RTL, verification, and implementation tasks on DECCANX projects such as the NX-AXI DMA engine and the 13-stage RISC-V core, working beside senior engineers and documenting what you learn.
Key Responsibilities
- Read design specifications and turn them into small RTL blocks and directed tests
- Run simulations, read waveforms and report what the design did versus what the spec said
- Assist with lint, synthesis, and static timing checks on small blocks
- Maintain clear notes: design decisions, test results and debug findings
- Take part in design and code reviews and respond to review comments
- Present a short technical summary of your rotation work each month
Requirements & Tech Stack
Skills Required
- Digital logic and sequential design: Strong FSMs, counters, FIFOs and timing basics appear in every task.
- Verilog or SystemVerilog: Working knowledge; you will read and write synthesizable RTL from the first month.
- Computer architecture basics: Working knowledge; pipelines, caches and buses give context to the blocks you build.
- Linux command line and Git: Working knowledge; all work lives in version-controlled repositories.
- Clear technical writing: Working knowledge; documentation is part of every deliverable.
Nice to have
- A small RTL project, even a UART or FIFO
- Basic scripting in Python or Bash
- Awareness of the ASIC flow stages
Tools you will use
- SystemVerilog
- Simulators such as Verilator or Icarus Verilog
- Waveform viewers
- Git
- Python
What you will learn
- The specification-to-timing flow
- How RTL, verification, and implementation teams hand work to each other
- Debugging methodically with waveforms and logs
Your first 90 days
- First 30 days: Set up the toolchain, read the project specs and complete a guided RTL exercise.
- Days 31 to 60: Own a small block with a testbench and a short review.
- Days 61 to 90: Present your rotation findings and pick a specialisation to deepen.
Who fits
You like understanding how things work end to end and would rather ask a precise question than guess.