ASIC Engineer, New Grad

About the Role

Join the Cisco Silicon One team to design and verify leading-edge multimillion gate ASICs. You will be involved in creating next-generation networking chips in advanced process nodes, driving the backend process through the entire RTL2GDS Implementation flow. This role is for the Physical Design team in Bangalore, India.

Key Responsibilities

• Driving the backend process through the entire RTL2GDS Implementation flow.
• Hierarchical floor planning.
• Place & route.
• Timing closure.
• Power integrity.
• Static timing verification.
• Physical verification and equivalence checks.
• Focus on performance & die size optimization.
• Designing and verifying leading-edge multimillion gate ASICs.

Requirements & Tech Stack

• Eligibility: 2027 graduates only.
• Project Management: Ability to manage multiple tasks and work toward long-term goals.
• Engineering Fundamentals: Solid understanding of engineering fundamentals, digital design fundamentals, and technical problem-solving skills.
• Collaboration: Experience in establishing and sustaining strong relationships with the extended team.
• Communication: Excellent communication skills (verbal and written).
• Physical Design Knowledge:
• Strong grasp of digital design, CMOS technology, VLSI principles, timing, and power fundamentals.
• Navigating the complete RTL to GDSII flow.
• Logic synthesis, floorplanning, placement, clock tree synthesis, routing, static timing analysis, and physical verification signoff.
• Understanding key metrics like setup and hold timing, clock skew, congestion, IR drop, electromigration, DRC, LVS, PVT corners, and SDC constraints.
• Solid scripting skills for automating workflows.
• Design/Verification Knowledge:
• Knowledge of hardware design and test/verification environments.
• Experience with UVM.
• Coursework in advanced data structures, algorithms, and design patterns.
• Languages such as SystemVerilog HDL, C, C++, and Python.
• Team-player, can-do attitude.

Qualifications

• 2027 graduates.
• Solid understanding of engineering fundamentals.
• Solid understanding of digital design fundamentals.
• Technical problem-solving skills.
• Experience in establishing and sustaining strong relationships with the extended team.
• Excellent communication skills (verbal and written).
• Strong grasp of digital design, CMOS technology, VLSI principles, timing, and power fundamentals.
• Comfortable navigating the complete RTL to GDSII flow.
• Solid scripting skills.
• Knowledge of hardware design and test/verification environments built using an object-oriented framework in UVM.
• Coursework in advanced data structures, algorithms, and design patterns.
• Proficiency in languages such as SystemVerilog HDL, C, C++, and Python.