ASIC Design Engineer

About the Role

Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design organization. Successful candidates will have the opportunity to contribute across a variety of projects spanning high-performance computing, AI, mobile, automotive, data center, and next-generation semiconductor technologies. Engineers in this role may work on different aspects of ASIC and SoC development, including architecture, RTL design, implementation, timing analysis, design methodology, automation, and silicon bring-up activities, depending on project needs and business priorities.

Key Responsibilities

• Participate in the architecture, design, implementation, integration, and optimization of ASIC, SoC, and IP solutions.
• Develop and validate design solutions that meet performance, power, area, timing, and quality objectives.
• Contribute to ASIC development activities including RTL design, static timing analysis, timing closure, synthesis, verification, and silicon bring-up, depending on project requirements.
• Collaborate closely with cross-functional teams including architecture, RTL design, physical design, verification, methodology, and software teams to deliver complex SoC solutions.
• Analyze and resolve design, implementation, and verification challenges using sound ASIC engineering practices.
• Participate in design reviews and contribute technical expertise to drive project execution and quality.
• Develop and enhance design flows, methodologies, automation frameworks, and engineering tools to improve productivity and quality.
• Support continuous improvement efforts by applying silicon learnings and feedback to future designs, processes, and methodologies.
• Effectively communicate technical concepts, collaborate across teams, and contribute to a strong engineering culture.

Requirements & Tech Stack

• Bachelor's degree in Science, Engineering, or related field.
• Experience in ASIC, FPGA, or SoC design and development.
• Understanding of digital design fundamentals, computer architecture, and semiconductor development processes.
• Experience with industry-standard ASIC design, implementation, verification, and/or timing analysis tools.
• Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.
• Strong analytical, problem-solving, communication, and teamwork skills.

Potential Project Areas

Depending on business needs and candidate background, project assignments may include:

• ASIC/SoC architecture and RTL design
• Implementation, constraints development, STA, and timing closure
• Synthesis, low-power design, and multi-voltage domain work
• Design methodology, flows, automation, and tool development
• IP integration, design verification support, and system simulation
• Silicon bring-up support and feedback into process or methodology improvements

Qualifications

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Experience in ASIC, FPGA, or SoC design and development.
• Understanding of digital design fundamentals, computer architecture, and semiconductor development processes.
• Experience with industry-standard ASIC design, implementation, verification, and/or timing analysis tools.
• Programming or scripting experience with languages such as Python, Tcl, Perl, or similar.
• Strong analytical, problem-solving, communication, and teamwork skills.

Preferred Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• Experience in one or more areas including RTL design, ASIC implementation, timing analysis, timing closure, verification, high-performance computing, AI/ML accelerators, data center technologies, low-power design, or silicon validation.
• Knowledge of modern SoC architectures, IP integration, and advanced process technologies.
• Experience designing arithmetic, computational, machine learning, server/data center, or related IPs.
• Experience developing tools, scripts, or automation to improve engineering productivity and design quality.