ASIC DFT Engineer I (Full Time)

About the Role

This role is within the Silicon One development organization as an ASIC Design for Test (DFT) Engineer I. The primary focus is on Design-for-Test. You will work with frontend RTL and backend Physical Design teams to understand chip architecture and drive DFT requirements early in the design cycle.

Key Responsibilities

• Implement Hardware Design-for-Test (DFT) features to support ATE, in-system test, debug, and diagnostics.
• Create and enhance automation scripts to improve implementation robustness and efficiency.
• Collaborate with Design, Design Verification, and Physical Design teams to enable integration and validation of test logic throughout the implementation and post-silicon validation flows.
• Validate test timing and logic equivalency of designs using SystemVerilog.
• Utilize ATPG and EDA tools (e.g., TestMax, Tetramax, Tessent, PrimeTime) for test pattern generation and analysis.

Requirements & Tech Stack

• Foundational understanding or academic/internship exposure to JTAG protocols, scan architectures, and BIST (including memory BIST and boundary scan).
• Familiarity or introductory hands-on exposure to EDA and ATPG tools.
• Scripting or coding skills in Python, Tcl, or Perl.
• Experience working with gate-level simulations and debugging using simulators like VCS.
• Practical experience or strong coursework in verification skills, including SystemVerilog, logic equivalency checking, and test-timing validation.
• Understanding of basic VLSI circuit physical behaviors (e.g., electromigration, temperature/voltage variation effects) and familiarity with basic timing concepts (setup/hold times, metastability).
• Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis.
• Strong verbal and written communication skills.

Qualifications

• A Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months).
• Qualifying education should be in ASIC DFT or a related field.