Design Engineer

About the Role

Micron Technology is a world leader in innovating memory and storage solutions. The Engineer – NVE Design role is a core technical individual contributor focused on the design and validation of on-chip controller and mixed-signal circuitry in NAND Flash devices. This position contributes to architecture development and product definition, builds verification strategies and test plans, and executes subsystem to full-chip verification across RTL, firmware, and Verilog environments.

Key Responsibilities

• Develop and review random-sequence testbench content by analyzing block-level specification documents for new and legacy features.
• Build, enhance, and support SVA/SystemVerilog assertion-based verification environments, including UVM testbenches, for subsystem and full-chip Verilog verification.
• Execute verification workflows including modeling and simulation using industry-standard simulators, and drive RTL code coverage and functional coverage closure.
• Implement, enhance, and support automation tools and workflows to improve design verification efficiency using scripting languages such as Perl and Python.
• Develop synthesizable NAND models to enable FPGA emulation of ASIC controller designs and contribute to cross-group communication and standardization.

Requirements & Tech Stack

• Bachelor’s degree or Master’s degree in Electrical Engineering or related field.
• Experience contributing to architecture development and product definition, test planning, system integration, and verification for controller and/or mixed-signal circuitry.
• Experience developing and supporting verification testbenches and assertions for subsystem and full-chip verification (SystemVerilog/SVA/Verilog and UVM).
• Experience with RTL code coverage and functional coverage analysis to meet coverage goals.
• Experience building or supporting automation pipelines or tooling in an engineering environment (e.g., Perl and/or Python).

Qualifications (Preferred)

• Understanding of at least one emulation platform such as Cadence Palladium, Mentor Veloce, or Synopsys Zebu.
• Experience performing emulation FPGA builds for SoC designs and evaluating tradeoffs among build size, emulation speed, and debuggability.
• Experience developing new transactors and hybrid emulation models.
• Familiarity with model evaluation, dataset creation, feature engineering, and using AI.
• Experience working with larger datasets using Python common ML/data libraries.

US base salary range: $86,000.00 - $173,000.00 a year. Additional Compensation May Include Benefits, Bonuses And Equity.