ASIC Design Engineer Intern (Video Silicon IP)
ByteDance
Posted 14 Nov 2026, 05:31 ET
This job at a glance
- Who can apply
- New grads and up to 1 year · Master's degree
- Must know
- Python
- Work
- On-site in San Jose · internship
- Pay
- Not stated by the employer.
- Skill demand
- Python7%of 150 similar entry-level jobs posted in the US this week
- Listed
- Nov 14, 2026 · still open
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About the Role
This is an internship opportunity within the Video Silicon IP team at ByteDance. The team is focused on building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC). Interns will gain hands-on experience, industry exposure, and opportunities to apply their knowledge to real-world challenges.
Key Responsibilities
- Work closely with architecture, algorithm, and verification teams to build high performance and low power video processing IPs.
- Apply knowledge of computer architecture and ASIC design to create ASIC design for compressing and processing still images and videos.
Requirements & Tech Stack
- ASIC Design
- Video Codecs
- RTL design (using SystemVerilog) or High Level Synthesis (HLS)
- UVM methodology, SystemC, or DPI
- Python for task automation
Qualifications
- Currently pursuing a Master's degree in Computer Science/Electrical Engineering or a related technical discipline.
- Knowledge of Video Codecs.
- Experience with RTL design (SystemVerilog) or High Level Synthesis (HLS).
- Experience with UVM methodology, SystemC, or DPI.
- Good programming skills in Python for task automation.
Candidates may apply to a maximum of two positions across the company and its affiliates globally. Applications are reviewed on a rolling basis; applying early is encouraged. Please clearly state your availability (start and end dates) in your resume.